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PRELIMINARY TECHNICAL DATA
a
MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62kB FLASH MCU
Preliminary Technical Data
FEATURES High Resolution Sigma-Delta ADCs Two Independent ADCs (24-Bit and 16-Bit Resolution) 24-Bit No Missing Codes, Primary ADC 21-Bit rms (18.5 Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/C, Gain Drift 0.5 ppm/C Memory 62 Kbytes On-Chip Flash/EE Program Memory 4 Kbytes On-Chip Flash/EE Data Memory Flash/EE, 100 Year Retention, 100 Kcycles Endurance 3 Levels of Flash/EE Program Memory Security In-Circuit Serial Download (No External Hardware) High Speed User Download (5 Seconds) 2304 Bytes On-Chip Data RAM 8051-Based Core 8051 Compatible Instruction Set High Performance Single Cycle Core 32 kHz External Crystal On-Chip Programmable PLL (12.58 MHz Max) 3 x 16-Bit Timer/Counter 26 Programmable I/O Lines 11 Interrupt Sources, Two Priority Levels Dual Data Pointer, Extended 11-Bit Stack Pointer On-Chip Peripherals Internal Power on Reset Circuit 12-Bit Voltage Output DAC Dual 16-Bit S-D DACs/PWMs On-Chip Temperature Sensor Dual Excitation Current Sources Time Interval Counter (Wakeup/RTC Timer) UART, SPI(R), and I2C(R) Serial I/O High Speed Baud Rate Generator (incl 115,200) Watchdog Timer (WDT) Power Supply Monitor (PSM) Power Normal: 2.3mA Max @ 3.6 V (Core CLK = 1.57 MHz) Power-Down: 20A Max with Wakeup Timer Running Specified for 3 V and 5 V Operation Package and Temperature Range 52-Lead MQFP (14 mm x 14 mm), -40C to +125C 56-Lead CSP (8 mm x 8 mm), -40C to +85C APPLICATIONS Intelligent Sensors WeighScales Portable Instrumentation, Battery Powered Systems 4-20mA Transmitters Data Logging Precision System Monitoring
REV. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
ADUC844
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION The ADUC844 is a complete smart transducer front end, integrating two high resolution sigma-delta ADCs, an 8-bit MCU, and program/data Flash/EE memory on a single chip. The two independent ADCs (primary and auxiliary) include a temperature sensor and a PGA (allowing direct measurement of low level signals). The ADCs with on-chip digital filtering and programmable output data rates are intended for the measurement of wide dynamic range, low frequency signals, such as those in weigh scale, strain-gage, pressure transducer, or temperature measurement applications. The device operates from a 32 kHz crystal with an on-chip PLL generating a high frequency clock of 12.58 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an optimized single cycle 8052 offering up to 12.58MIPs performance while maintaining the 8051 instruction set compatibility. 62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of nonvolatile Flash/EE data memory, and 2304 bytes of data RAM are provided on-chip. The program memory can be configured as data memory to give up to 60 Kbytes of NV data memory in data logging applications. On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADUC844 is supported by a QuickStartTM development system featuring low cost software and hardware development tools.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com (c) 2003 Analog Devices, Inc. All rights reserved.
PRELIMINARY TECHNICAL DATA
ADUC844 SPECIFICATIONS1
PARAMETER PRIMARY ADC Conversion Rate No Missing Codes2 Resolution Output Noise Integral Non Linearity Offset Error3 Offset Error Drift (vs. Temp) Full-Scale Error4 Gain Error Drift5 (vs. Temp) ADC Range Matching Power Supply Rejection Common Mode DC Rejection On AIN On AIN Common Mode 50/60Hz Rejection On AIN On AIN Normal Mode 50/60 Hz Rejection On AIN PRIMARY ADC ANALOG INPUTS Differential Input Voltage Ranges9,10 Bipolar Mode (ADC0CON.5 = 0) Unipolar Mode (ADC0CON.5 = 1) Analog Input Current2 Analog Input Current Drift Absolute AIN Voltage Limits2 EXTERNAL REFERENCE INPUTS REFIN(+) to REFIN(-) Range2 Average Reference Input Current Average Reference Input Current Drift `NO Ext. REF' Trigger Voltage Common Mode DC Rejection Common Mode 50/60Hz Rejection Normal Mode 50/60 Hz Rejection AGND + 0.1 1 5 15 MIN TYP 5.35 24 19.79
(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(-) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN, to TMAX unless otherwise noted.).
MAX
UNITS
CONDITION
105
13.5 18.5 See Tables X and XI in ADC Description 15 3 10 10 0.5 2 80 113 95 113 95 90 60
Hz Bits Bits Pk-Pk Bits Pk-Pk
ppm of FSR V nV/C V ppm/C V dBs dBs dBs dBs dBs dBs dBs
On Both Channels 19.79Hz Update Rate Range = 20mV, 20Hz Update Rate Range = 2.56V, 20Hz Update Rate Output Noise varies with selected Update Rates and Gain Range 1 LSB16
AIN=18mV AIN=1V, Range= 2.56V AIN=7.8mV, Range= 20mV @DC, AIN=7.8mV, Range= 20mV @DC, AIN=1V, Range= 2.56V 20 Hz Update Rate 50/60Hz 1Hz, AIN=7.8mV, Range= 20mV 50/60Hz 1Hz, AIN=1V, Range= 2.56V 50/60Hz 1Hz, 20 Hz Update Rate
1.024 x VREF/GAIN 0 a 1.024 x REFIN/GAIN 1 5
V V nA nA pA/C pA/C V V A/V nA/V/C V dBs dBs dBs
VREF = REFIN(+) - REFIN(-) (or Int 1.25V Ref) GAIN = 1 to 128 VREF = REFIN(+) - REFIN(-) GAIN=1 to 128 TMAX = 85C TMAX = 125C TMAX = 85C TMAX = 125C
AVDD - 0.1 AVDD
2.5 +/- 1 +/- 0.01
Both ADCs Enabled NOXREF bit active if VREF<0.3V NOXREF bit Inactive if VREF>0.65 @DC, AIN=1V, Range= 2.56V 50/60Hz 1Hz, AIN=1V, Range= 2.56V 50/60Hz 1Hz, 59.4 Hz Update Rate
0.3 125 90 60
0.65
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PRELIMINARY TECHNICAL DATA
ADUC844
PARAMETER AUXILIARY ADC No Missing Codes2 Resolution Output Noise Integral Non Linearity Offset Error3 Offset Error Drift Fullscale Error4 Gain Error Drift5 Power Supply Rejection Normal Mode 50/60 Hz Rejection On AIN On REFIN AUXILIARY ADC ANALOG INPUTS Differential Input Voltage Ranges9, 10 (Bipolar Mode - ADC0CON3 = 0) (Unipolar Mode - ADC0CON3 = 1) Average Analog Input Current Analog Input Current Drift Absolute AIN Voltage Limits2, 11 MIN 16 16 See Table XII 15 -2 1 -2.5 0.5 80 60 60 TYP MAX UNITS Bits Bits Pk-Pk ppm of FSR LSB V /C LSBs ppm/C dBs dBs dBs CONDITION 20 Hz Update Rate Range = 2.5V, 20Hz Update Rate Output Noise varies with selected Update Rates 1 LSB16
AIN=1V, Range= 2.56V 50/60Hz 1Hz, 19.79Hz Update Rate 50/60Hz 1Hz, 19.79Hz Update Rate
REFIN 0 a REFIN 125 2 AGND - 0.03 AVDD + 0.03
V V nA/V pA/V/C V
REFIN=REFIN(+)-REFIN(-) (or Int 1.25V Ref) REFIN=REFIN(+)-REFIN(-) (or Int 1.25V Ref)
ADC SYSTEM CALIBRATION Full Scale Calibration Limit Zero Scale Calibration Limit Input Span DAC Voltage Range Resistive Load Capactive Load Output Impedance ISINK DC Specifications7 Resolution Relative Accuracy Differential NonLinearity Offset Error Gain Error8 AC Specifications2,7 Voltage Output Settling Time Digital to Analog Glitch Energy
+1.05 x FS -1.05 x FS 0.8 x FS 2.1 x FS
V V V
0 a VREF 0 a AVDD 10 100 0.5 50
V V k pF A
DACCON.2 = 0 DACCON.2 = 1 From DAC Output to AGND From DAC Output to AGND
12 3 -1 50 1 1 15 10 LSBs Bit mV % % us nVs Guaranteed 12-Bit Monotonic AVDD Range VREF Range Setling time to 1LSB of final value 1 LSB change at major carry
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PRELIMINARY TECHNICAL DATA
ADUC844 SPECIFICATIONS1
PARAMETER INT REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco TEMPERATURE SENSOR Accuracy Thermal Impedance MIN TYP MAX UNITS CONDITION 1.237 1.25 45 100 2.5 50 100 1.2625 V dBs ppm/C V dBs ppm/C initial tolerance @ 25C, VDD=5V
2.475
1.525
initial tolerance @ 25C, VDD=5V
+/- 2 90 52
C C/W C/W
MQFP Package CSP Package
TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current AIN- Current Initial Tolerance at 25C Drift EXCITATION CURRENT SOURCES Output Current Initial Tolerance at 25C Drift Initial Current Matching at 25C Drift Matching Line Regulation (AVDD) Load Regulation Output Compliance POWER SUPPLY MONITOR (PSM) AVDD Trip Point Selection Range AVDD Trip Point Accuracy AVDD Trip Point Accuracy DVDD Trip Point Selection Range DVDD Trip Point Accuracy DVDD Trip Point Accuracy
-100 100 +/- 10 0.03
nA nA % %/C
AIN+ is the selected positive input to the primary ADC AIN- is the selected negative input to the primary ADC
-200 +/-10 200 +/-1 20 1 AGND 2.63 0.1 AVDD-0.6 4.63 +/- 3.0 +/- 3.0 4.63 +/- 3.0 +/- 3.0
A % ppm/C % ppm/C A/V V V V % % V % %
Available from each Current Source
Matching between both Current Sources AVDD=5V +/- 5%
2.63
Four Trip Points selectable in this range TMAX = 85C TMAX = 125C Four Trip Points selectable in this range TMAX = 85C TMAX = 125C
CRYSTAL OSCILLATOR (XTAL 1AND XTAL2) Logic Inputs, XTAL1 Only2 VINL, Input Low Voltage VINH, Input Low Voltage XTAL1 Input Capacitance XTAL2 Output Capacitance 3.5 2.5 18 18
0.8 0.4
V V V V pF pF
DVDD = 5V DVDD = 3V DVDD = 5V DVDD = 3V
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PRELIMINARY TECHNICAL DATA
ADUC844
PARAMETER LOGIC INPUTS All Inputs except SCLOCK, RESET and XTAL12 VINL, Input Low Voltage VINH, Input Low Voltage SCLOCK and RESET Only (Schmidt Triggered Inputs) 2 VT+ VTVT+ - VTInput Currents Port 0, P1.2aP1.7, EA SCLOCK, MOSI,MISO SS13 RESET 35 P1.0, P1.1, Port 2, Port 3 -180 -20 Input Capacitance LOGIC OUTPUTS All Digital Outputs except XTAL22 VOH, Output High Voltage VOL, Output Low Voltage14 5 2.0 MIN TYP MAX UNITS CONDITION
0.8 0.4
V V V
DVDD = 5V DVDD = 3V
1.3 0.95 0.8 0.4 0.3 2.0 -10
3.0 2.5 1.4 1.1 0.85
V V V V V V A A A A A A A A pF
DVDD = 5V DVDD = 3V DVDD = 5V DVDD = 3V DVDD = 5V or 3V
+/- 10 -40 +/-10 +/-10 105 +/-10 -660 -75
VIN = 0V or VDD VIN = 0V, DVDD=5V, Internal Pullup VIN = DVDD, DVDD=5V VIN = 0V, DVDD=5V VIN = DVDD, DVDD=5V, Internal Pull-Down VIN = DVDD, DVDD=5V VIN = 2V, DVDD=5V VIN = 0.45V, DVDD=5V All Digital Inputs
2.4 2.4 0.8 0.8 0.8 +/-10 5
Floating State Leakage Current Floating State Output Capacitance START UP TIME At Power On After External RESET in Normal Mode After WDT RESET in Normal Mode From Idle Mode From Power-Down Mode Oscillator Running Wakeup with INT0 Interrupt Wakeup with SPI Interrupt Wakeup with TIC Interrupt Wakeup with External RESET Oscillator Powered Down Wakeup with INT0 Interrupt Wakeup with SPI Interrupt Wakeup with External RESET
V V V V V A pF
DVDD = 5V, ISOURCE = 80 A DVDD = 3V, ISOURCE = 20 A ISINK = 8mA, SCLOCK, MOSI/SDATA ISINK = 10mA, P1.0, P1.1 ISINK = 1.6mA, All Other Outputs
300 3 3 10
ms ms ms us
Controlled via WDCON SFR
PLLCON.7 = 0 20 20 20 3 20 20 5 us us us us PLLCON.7 = 1 us us ms
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PRELIMINARY TECHNICAL DATA
ADUC844 SPECIFICATIONS1
PARAMETER MIN TYP MAX UNITS Cycles CONDITION FLAH/EE MEMORY RELIABILITY CHARACTERISTICS Endurance16 100,000 700,000 Data Retention17 100 POWER REQUIREMENTS Power Supply Voltages AVDD 3V Nominal AVDD 5V Nominal DVDD 3V Nominal DVDD 5V Nominal 5V POWER CONSUMPTION Normal Mode18, 19 DVDD Current 13 AVDD Current Power-Down Mode18, 19 DVDD Current DVDD Current AVDD Current Typical Additional Peripheral Currents (AIDD and D IDD) Primary ADC Auxiliary ADC Power Supply Monitor DAC Dual Excitation Current Sources 3V POWER CONSUMPTION Normal Mode18, 19 DVDD Current 8 AVDD Current Power-Down Mode18, 19 DVDD Current DVDD Current AVDD Current 10 80 1 3
2.7 4.75 2.7 4.75
3.6 5.25 3.6 5.25
V V V V 4.75V < DVDD <5.25V, AVDD= 5.25V
4 16 180 53 100 30 80 1 3
mA mA A A A A A A A mA mA A A A
core clock = 1.57MHz core clock = 12.58MHz
TMAX = 85C; Osc ON;TIC ON TMAX = 125C; Osc ON; TIC ON TMAX = 85C; Osc OFF TMAX = 125C; Osc OFF TMAX = 85C; Osc ON or OFF TMAX = 125C; Osc ON or OFF
1 0.5 50 150 400
4.75V < DVDD <5.25V, AVDD= 5.25V 2.3 10 180 20 40 mA mA A A A A A A A core clock = 1.57MHz core clock = 12.58MHz
TMAX = 85C; Osc ON;TIC ON TMAX = 125C; Osc ON; TIC ON Osc OFF TMAX = 125C; Osc OFF TMAX = 85C; Osc ON or OFF TMAX = 125C; Osc ON or OFF
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PRELIMINARY TECHNICAL DATA
ADUC844
NOTES 1 Temperature Range for ADUC844BS (MQFP package) is -40C to +125C. Temperature Range for ADUC844BCP (CSP package) is -40C to +85C. These numbers are not production tested but are guaranteed by design and/or characterization data on production release. System Zero-Scale Calibration can remove this error. The primary ADC is factory calibrated at 25C with AVDD = DVDD = 5 V yielding this full-scale error of 10 V. If user power supply or temperature conditions are significantly different from these, an Internal Full-Scale Calibration will restore this error to 10 V. A system zero-scale and full-scale calibration will remove this error altogether. Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input. The auxiliary ADC is factory calibrated at 25C with AVDD = DVDD = 5 V yielding this full-scale error of -2.5 LSB. A system zero-scale and full-scale calibration will remove this error altogether. DAC linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to VREF, reduced code range of 100 to 3950, 0 to VDD. Gain Error is a measure of the span error of the DAC. In general terms, the bipolar input voltage range to the primary ADC is given by RangeADC = (VREF 2RN )/125, where: VREF = REFIN(+) to REFIN(-) voltage and VREF = 1.25 V when internal ADC VREF is selected. RN = decimal equivalent of RN2, RN1, RN0 e.g., VREF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the RangeADC = 1.28 V, In unipolar mode, the effective range is 0 V to 1.28 V in our example.
2 3 4
5 6
7 8 9
10 1.25 V is used as the reference voltage to the ADC when internal VREF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively. 11 In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND - 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar range is still -VREF to +VREF; however, the negative voltage is limited to -30 mV. 12 The ADUC844BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating. 13 Pins configured in SPI Mode, pins configured as digital inputs during this test. 14 Pins configured in I2C Mode only. 15 Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory. 16 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at -40 C, +25C, +85C, and +125C. Typical endurance at 25C is 700 Kcycles. 17 Retention lifetime equivalent at junction temperature (TJ) = 55C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section of this data sheet. 18 Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions: Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop. Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode. Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2-P1.7 Pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR. 19 DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice
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PRELIMINARY TECHNICAL DATA
ADUC844
ABSOLUTE MAXIMUM RATINGS (TA = 25C unless otherwise noted) AVDD to AGND AVDD to DGND DVDD to AGND DVDD to DGND AGND to DGND2 AVDD to DVDD Analog Input Voltage to AGND3 Reference Input Voltage to AGND AIN/REFIN Current (Indefinite) Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Storage Temperature Range Junction Temperature JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec)
PIN CONFIGURATION
-0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +0.3 V -2 V to +5 V -0.3 V to AVDD +0.3 V -0.3 V to AVDD +0.3 V 30 mA -0.3 V to DVDD +0.3 V -0.3 V to DVDD +0.3 V -40C to +125C -65C to +150C 150C 90C/W 215C 220C
52-Lead MQFP
52 40
1
P IN 1 IN D E N TIF IE R
39
A D u C8 34 T OP V IE W (No t t o S c a l e)
13
27
14
26
56-Lead CSP
56 1
PIN 1 INDEN TIFIER
43 42
1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2AGND and DGND are shorted internally on the ADUC844. 3Applies to P1.2 to P1.7 pins operating in analog or digital input modes.
ADuC834 TOP VIEW (Not to Scale)
14 15 28
29
ORDERING GUIDE MODEL ADUC844BS62-5 ADUC844BS62-3 ADUC844BCP62-5 ADUC844BCP62-3 ADUC844BCP32-5 ADUC844BCP32-3 ADUC844BCP8-5 ADUC844BCP8-3 EVAL-ADUC844QS EVAL-ADUC844QS Temperature Range (oC) -40 a+125 -40 a+125 -40 a+125 -40 a+125 -40 a+125 -40 a+125 -40 a+125 -40 a+125 Voltage Range (V) 4.75 a 5.25 2.75 a 3.60 4.75 a 5.25 2.75 a 3.60 4.75 a 5.25 2.75 a 3.60 4.75 a 5.25 2.75 a 3.60 User Code Space 62 kBytes 62 kBytes 62 kBytes 62 kBytes 32 kBytes 32 kBytes 8 kBytes 8 kBytes Package Description 52-Lead Plastic Quad Flatpack 52-Lead Plastic Quad Flatpack 56-Lead Chip Scale Package 56-Lead Chip Scale Package 56-Lead Chip Scale Package 56-Lead Chip Scale Package 56-Lead Chip Scale Package 56-Lead Chip Scale Package QuickStart Development System QuickStart Plus Development System Package Option S-52 S-52 S-52 S-52 S-52 S-52 S-52 S-52
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADUC844 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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PRELIMINARY TECHNICAL DATA
ADUC844
PIN FUNCTION DESCRIPTIONS Pin No: 52-MQFP 1, 2 Pin No: 56-CSP 56, 1 Pin Mnemonic P1.0/P1.1 I/O P1.0 and P1.1 can function as a digital inputs or digital outputs and have a pullup configuration as described below for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10mA. P1.0 and P1.1 also have various secondary functions as described below. P1.0 can also be used to provide a clock input to Timer 2. When enabled, counter 2 is incremented in response to a negative transition on the T2 input pin. If the PWM is enabled, the PWM0 output will appear at this pin. P1.1 can also be used to provide a control input to Timer 2. When enabled, a negative transition on the T2EX input pin will cause a Timer 2 capture or reload event. If the PWM is enabled, the PWM1 output will appear at this pin. Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input for which `0' must be written to the port bit. As a digital input, these pins must be driven high or low externally. These pins also have the following analog functionality: The voltage output from the DAC or one or both current sources (200 uA or 2 x 200 uA) can be configured to appear at this pin. Auxiliary ADC Input or one or both current sources can be configured at this pin. Primary ADC, Positive Analog Input Primary ADC, Negative Analog Input Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage Analog Supply Voltage Analog Ground. A second Analog ground is provided with the CSP version only. External Reference Input, negative terminal External Reference Input, positive terminal The slave select input for the SPI Interface is present at this pin. A weak pull-up is present on this pin. Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this input pin. Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin. Type* Description
P1.0/T2/PWM0
I/O
P1.1/T2EX/PWM1
I/O
3a4 9 a 12
2 a3 11 a14
P1.2 aP1.7
I
P1.2/DAC/IEXC1 P1.3/AIN5/IEXC2 P1.4/AIN1 P1.5/AIN2 P1.6/AIN3 P1.7/AIN4/DAC 5 6 N/C 7 8 13 14 15 4 5 6 7 8 15 16 17 AVDD AGND AGND REFINREFIN+ SS MISO RESET
I/O I/O I I I I/O S S S I I I I I
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ADUC844
Pin No: 52-MQFP 16-19 22-25 Pin No: 56-CSP 18-21 24-27 Pin Mnemonic P3.0 a P3.7 I/O P3.0-P3.7 are bi-directional port pins with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle. Port 3 pins also have various secondary functions described below. Receiver Data for UART serial Port Transmitter Data for UART serial Port External Interrupt 0. This pin can also be used as a gate control input to Timer0. External Interrupt 1. This pin can also be used as a gate control input to Timer1. Timer/Counter 0 External Input If the PWM is enabled, an external clock may be input at this pin. Timer/Counter 1 External Input External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory. External Data Memory Read Strobe. Enables the data from an external data memory to Port 0. Digital Supply Voltage Digital Ground. Serial interface clock for either the I2C or SPI interface. As an input, this pin is a Schmitt-triggered input and a weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. Serial Data I/O for the I2C Interface or Master Output/Slave Input for the SPI Interface. A weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. Input to the crystal oscillator inverter. Output from the crystal oscillator inverter. (see "Hardware Design Considerations" for description) External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh. When held low this input enables the device to fetch all instructions from external program memory. To determine the mode of code execution, i.e., internal or external, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle. EA may also be used as an external emulation I/O pin and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution. Type* Description
16 17 18 19 22 23 24 25
18 19 20 21 24 25 26 27
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0/PWMCLK P3.5/T1 P3.6/WR P3.7/RD
20, 34, 48 21, 35, 47 26
22, 36, 51 23, 37, 50 28
DVDD DGND SCLOCK
S S I/O
27
29
MOSI/SDATA
I/O
28 a 31 36 a 39
30 a 32 38 a 42
P2.0 a P2.7
I/O
32 33
34 35
XTAL1 XTAL2 EA
I O
40
43
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PRELIMINARY TECHNICAL DATA
ADUC844
Pin No: 52-MQFP 41 Pin No: 56-CSP 44 Pin Mnemonic PSEN Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle. Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. It is activated every six oscillator periods except during an external data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR. I/O P0.0-P0.7, these pins are part of Port0 which is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. An external pull-up resistor will be required on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s. Type* Description
42
45
ALE
43 a 46 49 a 52
46 a 49 52 a 55
P0.0 a P0.7
*I = Input, O = Output, S = Supply.
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PRELIMINARY TECHNICAL DATA
ADUC844
DETAILED BLOCK DIAGRAM WITH PIN NUMBERS
Figure 1: Detailed Block Diagram of the ADUC844
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ADUC844
7FH
MEMORY7 ORGANISATION The ADUC844 contains 4 different memory blocks namely: - 62kBytes of On-Chip Flash/EE Program Memory - 4kBytes of On-Chip Flash/EE Data Memory - 256 Bytes of General Purpose RAM - 2kBytes of Internal XRAM (1) Flash/EE Program Memory The ADUC844 provides 62kBytes of Flash/EE program memory to run user code. The user can choose to run code from this internal memory or run code from an external program memory. If the user applies power or resets the device while the EA pin is pulled low externally, the part will execute code from the external program space, otherwise if EA is pulled high externally the part defaults to code execution from its internal 62kBytes of Flash/EE program memory. The ADUC844 does not support the rollover from F7FFh in internal code space to F800h in external code space. Instead the 2048 bytes between F800h and FFFFh will appear as NOP instructions to user code. Permanently embedded firmware allows code to be serially downloaded to the 62kBytes of internal code space via the UART serial port while the device is in-circuit. No external hardware is required. 56kBytes of the program memory can be repogrammed during runtime hence the code space can be upgraded in the field using a user defined protocol or it can be used as a data memory. This will be discussed in more detail in the Flash/EE Memory section of the datasheet. (2) Flash/EE Data Memory 4kBytes of Flash/EE Data Memory are available to the user and can be accessed indirectly via a group of registers mapped into the Special Function Register (SFR) area. Access to the Flash/EE Data memory is discussed in detail later as part of the Flash/EE memory section in this data sheet. (3) General Purpose RAM The general purpose RAM is divided into two seperate memories, namely the upper and the lower 128 bytes of RAM. The lower 128 bytes of RAM can be accessed through direct or indirect addressing while the upper 128 bytes of RAM can only be accessed through indirect addressing as it shares the same address space as the SFR space which can only be accessed through direct addressing. The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 16 bytes (128 bits), locations 20Hex through 2FHex above the register banks, form a block of directly addressable bit locations at bit addresses 00H through 7FH. The stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes. Reset initializes the stack pointer to location 07 hex. Any call or push pre-increments the SP before loading the stack. Hence loading the stack starts from locations 08 hex which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of RAM not used for data storage.
GENERAL-PURPOSE AREA 30H 2FH BANKS SELECTED VIA BITS IN PSW 11 18H 17H 10 10H 0FH 01 08H 07H 00 00H RESET VALUE OF STACK POINTER FOUR BANKS OF EIGHT REGISTERS R0 R7 20H 1FH BIT-ADDRESSABLE (BIT ADDRESSES)
Figure 2. Lower 128 Bytes of Internal Data Memory (4) Internal XRAM The ADUC844 contains 2kBytes of on-chip extended data memory. This memory although on-chip is accessed via the MOVX instruction. The 2kBytes of internal XRAM are mapped into the bottom 2kBytes of the external address space if the CFG844.0 bit is set, otherwise access to the external data memory will occur just like a standard 8051. Even with the CFG844.0 bit set access to the external XRAM will occur once the 24 bit DPTR is greater than 0007FFH.
FFFFFFH FFFFFFH
EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE)
EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE)
000800H 0007F FH 2 KBYTE S ON-CHIP XRAM
000000H CFG845.0=0
000000 H
CFG845.0=1
Figure 3: Internal and External XRAM When accessing the internal XRAM the P0, P2 port pins as well as the RD and WR strobes will not be output as per a standard 8051 MOVX instruction. This allows the user to use these port pins as standard I/O. The upper 1792 bytes of the internal XRAM can be configured to be used as an extended 11-bit stack pointer. By default the stack will operate exactly like an 8052 in that it will rollover from FFh to 00h in the general purpose RAM. On the ADUC844 however it is possible (by setting CFG844.7) to enable the 11-bit extended stack pointer. In this case the stack will rollover from FFh in RAM to 0100h in XRAM.
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ADUC844
The 11-bit stack pointer is visable in the SP and SPH SFRs. The SP SFR is located at 81h as with a standard 8052. The SPH SFR is located at B7h. The 3 LSBs of this SFR contain the 3 extra bits necessary to extend the 8-bit stack pointer into an 11-bit stack pointer.
07FFH
SPECIAL FUNCTION REGISTERS (SFRs) The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on chip peripherals. A block diagram showing the programming model of the ADUC844 via the SFR area is shown in Figure 5. All registers except the Program Counter (PC) and the four generalpurpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals.
62 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE PROGRAM MEMORY 4 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE DATA MEMORY 128-BYTE SPECIAL FUNCTION REGISTER AREA
UPPER 1792 BYTES OF ON-CHIP XRAM (DATA +STACK FOR EXSP=1, DATA ONLY FOR EXSP=0) CFG845.7 = 0 CFG845.7 = 1
100 H FFH 256 BYTES OF ON-CHIP DATA RAM (DATA + STACK) 00H 00H LOWER 25 6 BYTES OF ON-CHIP XRAM (DATA ONLY)
805 1COMPATIBLE CORE
DUAL SIGMA-DELTA ADCs
OTHER ON-CHIP PERIPHERALS 256 BYTES RAM 2K XRAM TEMP SENSOR CURRENT SOURCES 12-BIT DAC SERIAL I/O WDT, PSM TIC, PLL
Figure 4. Extended Stack Pointer Operation External Data Memory (External XRAM) Just like a standard 8051 compatible core the ADUC844 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. The ADUC844 however, can access up to 16MBytes of extrenal data memory. This is an enhancement of the 64kBytes external data memory space available on a standard 8051 compatible core. The external data memory is discussed in more detail in the ADUC844 Hardware Design Considerations section.
Figure 5. Programming Model Accumulator SFR (ACC) ACC is the Accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulatorspecific instructions refer to the Accumulator as A. B SFR (B) The B register is used with the ACC for multiplication and division operations. For other instructions it can be treated as a generalpurpose scratchpad register. Data Pointer (DPTR) The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte) and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL). The ADUC844 supports dual data pointers. Refer to the Dual Data Pointer section later in this datasheet. Stack Pointer (SP and SPH) The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the `top of the stack.' The SP register is incremented before data is stored during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP register is initialized to 07H after a reset. This causes the stack to begin at location 08H. As mentioned earlier the ADUC844 offers an extended 11-bit stack pointer. The 3 extra bits to make up the 11-bit stack pointer are the 3 LSBs of the SPH byte located at B7h. To enable the SPH SFR the
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EXSP (CFG844.7) bit must be set otherwise the SPH SFR cannot be read or written to. Program Status Word (PSW) The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I. SFR Address D0H Power ON Default Value 00H Bit Addressable Yes Bit 7 6 5 4 3 Name CY AC F0 RS1 RS0 Table I. PSW SFR Bit Designations Description Carry Flag Auxiliary Carry Flag General-Purpose Flag Register Bank Select Bits RS1 RS0 Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 Overflow Flag General-Purpose Flag Parity Bit The CFG844 SFR contains the necessary bits to configure the internal XRAM and the extended SP. By default it configures the user into 8051 mode. i.e. extended SP is disabled, internal XRAM is disabled. SFR Address AFhH Power ON Default Value 00H Bit Addressable No Bit 7 Name EXSP Table III. CFG844 SFR Bit Designations Description Extended SP Enable If this bit is set then the stack will rollover from SPH/SP = 00FFh to 0100h. If this bit is clear then the SPH SFR will be disabled and the stack will rollover from SP=FFh to SP =00h ------------------------------------XRAMEN XRAM Enable Bit If this bit is set then the internal XRAM will be mapped into the lower 2kBytes of the external address space. If this bit is clear then the internal XRAM will not be accessible and the external data memory will be mapped into the lower 2kBytes of external data memory. (see figure 3)
2 1 0
OV F1 P
6 5 4 3 2 1 0
The PCON SFR contains bits for power-saving options and generalpurpose status flags as shown in Table II. SFR Address Power ON Default Value Bit Addressable Bit 7 6 5 4 3 2 1 0 87H 00H No
Table II. PCON SFR Bit Designations Name Description SMOD Double UART Baud Rate SERIPD SPI Power-Down Interrupt Enable INT0PD INT0 Power-Down Interrupt Enable ALEOFF Disable ALE Output GF1 General-Purpose Flag Bit GF0 General-Purpose Flag Bit PD Power-Down Mode Enable IDL Idle Mode Enable
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ADUC844
COMPLETE SFR MAP Figure 5 below shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations in the SFR address space are not implemented; i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software.
* CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES. (1) THESE SFRS MAINTAIN THEIR PRE-RESET VALUES AFTER A RESET IF TIMECON.0=1. SFR MAP KEY: THESE BITS ARE CONTAINED IN THIS BYTE. BIT MNEMONIC BIT BIT ADDRESS RESET DEFAULT BIT VALUE SFR NOTE: SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE. IE0
89H
IT0
0 88H 0
TCON
88H 00H
MNEMONIC RESET DEFAULT VALUE SFR ADDRESS
Figure 6: Complete SFR Map
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ADUC844
INTRODUCTION The ADUC844 is a pin compatible upgrade to the ADuC834 provide increased core performance. The ADUC844 has a single cycle 8052 core allow operation at up to 12.58MIPs. It has all the same features as the ADuC834 but the standard 12-cycle 8052 core has been replaced with a 12.6MIPs single cycle core. Since the ADUC844 and ADuC834 share the same feature set only the differences between the two chips are documented here. For full documentation on the ADuC834 please consult the datasheet available at http://www.analog.com/microconverter 8052 Instruction Set The following pages document the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles resulting in 12.6MIPs peak performance when operating at PLLCON = 00H. Timer Operation Timers on a standard 8052 increment by one with each machine cycle. On the ADuC842 one machine cycle is equal to one clock cycle hence the timers will increment at the same rate as the core clock. INSTRUCTION TABLE TABLE IV: Optimized Single Cycle 8051 Instruction Set Mnemonic Arithmetic ARITHMETIC ADD A,Rn ADD A,@Ri ADDC A,Rn ADDC A,@Ri ADD A,dir ADD A,#data SUBB A,Rn SUBB A,@Ri SUBB A,dir SUBB A,#data INC A INC Rn INC @Ri INC dir INC DPTR DEC A DEC Rn DEC @Ri DEC dir MUL AB DIV AB DA A Description Add register to A Add indirect memory to A Add register to A with carry Add indirect memory to A with carry Add direct byte to A Add direct byte to A with carry Subtract register from A with borrow Subtract indirect memory from A with borrow Subtract direct from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment indirect memory Increment direct byte Increment data pointer Decrement A Decrement Register Decrement indirect memory Decrement direct byte Multiply A by B Divide A by B Decimal Adjust A Bytes 1 1 1 1 2 2 1 1 2 1 1 1 1 2 1 1 1 1 2 1 1 1 Cycles 1 2 1 2 2 2 1 2 2 1 1 1 2 2 3 1 1 2 2 9 9 2 ALE The output on the ALE pin on the ADuC834 was a clock at 1/6th of the core operating frequency. On the ADUC844 the ALE pin operates as follows. For a single machine cycle instruction: ALE is high for the first half of the machine cycle and low for the second half. The ALE output is at the core operating frequency.For a two or more machine cycle instruction: ALE is high for the first half of the first machine cycle and then low for the rest of the machine cycles. External Memory Access There is no support for external program memory access on the ADUC844. When accessing external RAM the EWAIT register may need to be programmed in order to give extra machine cycles to MOVX commands. This is to account for differing external RAM access speeds.
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ADUC844
Mnemonic Arithmetic LOGIC ANL A,Rn ANL A,@Ri ANL A,dir ANL A,#data ANL dir,A ANL dir,#data ORL A,Rn ORL A,@Ri ORL A,dir ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,@Ri XRL A,#data XRL dir,A XRL A,dir XRL dir,#data CLR A CPL A SWAP A RL A RLC A RR A RRC A BOOLEAN CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C Description AND register to A AND indirect memory to A AND direct byte to A AND immediate to A AND A to direct byte AND immediate data to direct byte OR register to A OR indirect memory to A OR direct byte to A OR immediate to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR indirect memory to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR indirect memory to A Exclusive-OR immediate data to direct Clear A Complement A Swap Nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry Clear carry Clear direct bit Set Carry Set direct bit Complement carry Complement direct bit AND direct bit and carry AND direct bit inverse to carry OR direct bit and carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit Bytes 1 1 2 2 2 3 1 1 2 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 2 2 2 Cycles 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 2 2 2
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Mnemonic Arithmetic BRANCHING JMP @A+DPTR RET RETI ACALL addr11 AJMP addr11 SJMP rel JC rel JNC rel JZ rel JNZ rel DJNZ Rn,rel LJMP LCALL addr16 JB bit,rel JNB bit,rel JBC bit,rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ dir,rel MISCELLANEOUS NOP Description Jump indirect relative to DPTR Return from subroutine Return from interrupt Absolute jump to subroutine Absolute jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on accumulator = 0 Jump on accumulator != 0 Decrement register, jnz relative Long jump unconditional Long jump to subroutine Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Compare A, direct JNE relative Compare A, immediate JNE relative Compare register, immediate JNE relative Compare indirect, immediate JNE relative Decrement direct byte, JNZ relative No operation Bytes 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 1 Cycles 3 4 4 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 1
Notes: 1. One cycle is one clock. 2. Cycles of MOVX instructions are 4 cycles when they have 0 wait state. Cycles of MOVX instructions are 4+N cycles when they have N wait states. 3. Cycles of LCALL instruction are 3 cycles when the LCALL instruction comes from interrupt.
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